You can use Microchip's low-cost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock ...

November 29, 2018 -- Morgan Hill, California—Perceptia Devices, Inc., a developer of innovative PLL and timing technology, today announced that its flagship high-end second-generation digital PLL has ...

RF absorption and PLL phase calibration help phased-array subsystems reduce clock spurs while preserving spectral purity and ...

RF synthesis is a critical function in today's electronic communications systems. Two of the technologies used for RF synthesis are phase locked loop (PLL) and direct digital synthesis (DDS). Each has ...

Imec, Rohm and Holst Centre showed off an all-digital PLL for IoT radio transceivers at the 2017 ISSCC. Whereas a PLL is traditionally one of the major power consumers in a radio and can take up to 30 ...

Los Altos, California, June 23, 2025 -- True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries ...

Scientists at Tokyo Institute of Technology have developed an advanced phase-locked loop[1] (PLL) frequency synthesizer that can drastically cut power consumption. This digital PLL could be an ...

Thanks to a digital phase-locked loop (DPLL), the ZL30109 DS1/E1 System Synchronizer chip brings timing and synchronization to multitrunk DS1 and E1 transmission equipment. DPLLs typically use a DSP ...

Corporation THAT Corporation, founded in 1989, designs, manufactures, and sells high-performance (until now, mostly) analog integrated circuits for professional audio manufacturers. Besides the new ...

Imec, Rohm and Holst Centre showed off an all-digital PLL for IoT radio transceivers at the 2017 ISSCC. Whereas a PLL is traditionally one of the major power consumers in a radio and can take up to 30 ...