Semiconductor Engineering

DFT At The Leading Edge

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed ...
Semiconductor Engineering

Testing The Stack: DFT Is Ready For 3D Devices

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area ...
Electronic Design

Where Is DFT Heading?

Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...
Electronic Design

CTL: The New Language of DFT

What is CTL, and why is it important to the semiconductor industry? The answers are here. Although the IEEE 1450.0 Stand-ard Test Interface Language (STIL) was adopted in March 1999, widespread ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...